1. Field of the Invention
The present invention relates to a driving circuit for generating the voltage control signals, in particular, to a driving circuit capable of reducing cost and solving the timing control problems.
2. Description of the Related Art
The driving circuit of a conventional display contains a positive power voltage and a negative power voltage, thereby increasing the operating voltage range of the circuit. In general, the driving circuit converts a low voltage signal to a high voltage signal by using the level shifter. For example, if the maximum operating voltage of the analog circuit is 6 volt while the voltage of the digital circuit is 1.5 volt, when a voltage signal to be transmitted from the digital circuit to the analog circuit, the voltage level must be converted.
In practice, the general MOS analog circuit can withstand such a voltage difference for the conversion from 1.5 volt to 6 volt. However, when the 1.5 volt to be converted to a negative voltage of −6 volt, such a voltage difference will exceed the capability of maximum voltage stress for the MOS device.
Some developers use the high voltage components in MOS analog circuits, such as ±15 volt, in order to withstand the aforesaid voltage difference. However, if using a large amount of high voltage components, not only more space but also additional cost is required.
In addition, the developers try to provide an intermediate voltage level (VCL) between 1.5 volt and −6 volt and try to solve the problems of the voltage stress and the timing of the power level in the MOS analog circuit. That is, the intermediate voltage level is usually generated by the analog negative power voltage (AVEE), and the intermediate voltage level is about −2.5 volt. However, in practice, the activating time of the intermediate voltage level will be after the activating time of the analog negative power voltage. In other words, if the digital circuit uses the intermediate voltage level to transmit the activating control signal of the analog negative power voltage, the activation of the analog negative power voltage will fail. Therefore, the approach of using the intermediate voltage level still has some timing problems in the system application.